Neuron with well-designed ionic system

Abstract

Neurons have an ionic system with several types of ion pumps and ion channels on their membranes. Each ion pump creates a specific difference in ion concentration inside and outside the neuron, and the energy resulting from this difference in concentration is maintained inside the neuron as a resting potential. Each ion channel senses the necessary situation, opens the channel, and allows the corresponding ion to pass through to perform its corresponding role. This ionic system realizes important functions such as (i) fast conduction of action potentials, (ii) achieving synaptic integration in response to several inputs with a time lag, and (iii) the information processing functions by neural circuits. However, the mechanisms by which these functions are realized have remained unclear. Therefore, based on the reports on various highly polymeric ion pumps, ion channels, cell membranes, and other components that have been elucidated so far, author analyzed how this ionic system can realize the above important functions from an electrical circuit designer point of view. As a result of a series of analyses, it was found that neurons realize each function by making full use of high-density packaging technology based on basic electrical principles and making maximum use of the extremely high dielectric properties of the ionic fluid of neurons. In other words, neuron looks to equip well designed ionic system which is the collaboration by designers of proteins and membranes that perform advanced functions and designers of electrical circuits that utilize them to achieve important functions electrically.

Keywords: capacitance; conduction velocity; dielectric constant; neural circuits; synaptic integration.

Figure 1

Equivalent circuit of an axon. (a) Conventional axon equivalent circuit. (b) Equivalent circuit with axial capacitance C1 added. Both circuits are distributed constant circuits, and the circuit parameters axial resistance R1 (3,500 MΩ/m), axon membrane resistance R2 (0.32 MΩm), and axon membrane capacitance C2 (1,300 pF/m) were set by converting the values compiled by A. L. Hodgkin (1964) to a diameter of 20 μm [1,22].

Figure 2

(a) Sum of EPSPs under t <˂ T. (b) Sum of EPSP under t >> T. (c) Membrane potential is increased by sum of Ca²⁺ions restrained in the spines and EPSPs [3].

Figure 3

Diagram of the capacitance connection for the charge in the spine. Csm is the spine membrane capacitance, Cn is the spine neck capacitance, Cd is the axial capacitance of the dendrite, Csp is the spine capacitance, Cdm is the dendrite membrane capacitance, and Csom is the soma membrane capacitance. n out of m spines hold excess Ca²⁺ ions. The series membrane capacitance Cns is composed of the series connection of Cn, Csp, and Csm, and the series capacitance Cs is composed of the series connection of Cn, Cd, and the total membrane capacitance ΣCm [3].

Figure 4

Circuit symbols and operations of digital circuit. (a); AND circuit outputs 1, only when all inputs are 1. (b); NAND circuit outputs 0, only when all inputs are 1.

Figure 5

Circuit symbols and operations of neural circuits. (a); Excitatory neuron outputs an excitatory neurotransmitters when the conditions for synaptic integration are met. (b); Inhibitory neuron outputs inhibitory neurotransmitters when the conditions for synaptic integration are met. In both circuits, short line segments connected to dendrite represent spines. Number in the soma indicates thresholds. Circles on spines, dendrites, soma, and axon terminals represent inhibitory receptors those receive the output of inhibitory neurons [4].

Figure 6

Digital circuits for basic operations. (a); Truth table for each basic logical operation. (b); Digital circuit for each basic logical operation using NAND elements [4].

Figure 7

Neural circuits for basic operations. (a); Truth table for each operation. (b); Neural circuit for each operation.

Figure 8

Encoder circuit. (a); Digital encoder circuit. (b); Neural encoder circuit [4].

Figure 9

Decoder circuit. (a); Digital decoder circuit. (b); Neural decoder circuit [4].

Figure 10

Contour detection circuits. (a); Digital contour detection circuit using an EOR function. (b); Neural contour detection circuit using an EOR function. (c); Neural contour detection circuit using a subtraction function [4].

Figure 11

Images of a square, a cross, a triangle, and a diagonal line on the V-plane [4].

Figure 12

Contours on the W plane. (a); Contours generated by a digital circuit. (b); Contours generated by a neural circuit [4].