High-Performance Silicon Nanowire Reconfigurable Field Effect Transistors Using Flash Lamp Annealing

Abstract

Top-down fabrication of reconfigurable field effect transistors (RFET) is a prerequisite for large-scale integration. Silicon (Si) nanowire-based RFET devices have been extensively studied in the past decade. To achieve superior RFET performance, it is necessary to develop scalable devices with controlled silicidation of the channels, a high on-off ratio, and symmetrical p- and n- on-currents. In this work, we present the electrical performance of scalable RFET devices based on Si nanowires featuring controlled silicide lengths attained through millisecond-range flash lamp annealing (FLA). The electronic properties of the transistors are optimized by tuning the different gate schemes and gate dielectric materials for nanowire passivation. We explore gate capacitive control on the energy bands in the conduction of charge carriers using various dielectric materials. The transfer characteristics of a single top-gated device with SiO₂ as gate dielectric show enhanced ambipolar behavior with negligible hysteresis, low subthreshold swing values of 210 mV/dec, and an on-off ratio (I _ON/I _OFF) of up to ∼10⁸ (8 orders of magnitude). The devices also demonstrate excellent electron and hole symmetry values with a record pn on-current symmetry of 1.03. Utilizing high-performance, scalable RFET devices with elevated symmetrical on-currents holds great promise for reducing delay and power consumption in future energy-efficient integrated circuitry.

Figure 1

SiO₂ passivated single-nanowire-based device: (a) back-gated transfer characteristics before and after FLA; the blue curve appears discontinued as the butterfly sweep terminates at V_BG = 0 V, reflecting the measurement protocol. The red curve’s discontinuity in the range V_BG = −10 to 0 V arises from noisy off-currents, which were excluded from the computation for clarity. (b) Cross section of the device after FLA with the voltage naming scheme. (c) SEM micrograph of the device.

Figure 2

Single top-gated devices with SiO₂ and Al₂O₃ passivation. Cross-sectional layout of the measurement scheme for (a) SiO₂ passivated device; (b) SiO₂ and Al₂O₃ passivated device. Top-view SEM micrograph of (c) a SiO₂ passivated single-nanowire device with a single top gate; (d) a SiO₂ passivated nanowire array-based device with a single top gate; and (e) a SiO₂ and Al₂O₃ passivated single-nanowire device with a single top gate. (f) Comparison of SiO₂ and Al₂O₃ shell-based devices showing the transfer characteristics of three different device types. (g) Histograms comparing the pn current symmetry and I_ON/I_OFF ratios.

Figure 3

Transfer characteristics shift analysis of the single-nanowire-based device with a SiO₂ shell. The different shifts in the transfer curve are seen with (a) positive and (b) negative values of V_DS. The length and width of the nanowire are 2.5 μm and 25 nm, respectively. (c) and (d) Band diagrams illustrating the drain-sideband bending in the single-nanowire-based device for incrementing V_DS values. (c) At V_TG > 0 V and V_DS = 0.25 V, band bending occurs predominantly at the drain side, facilitating electron conduction. As the positive V_DS increases, the field coupling intensifies, narrowing the energy barrier at the drain side and shifting the off-state current for the n-branch. (d) At V_TG < 0 V and V_DS = −0.25 V, the electric field coupling at the drain side increases due to the negative V_DS, causing a reduction in the barrier width. This promotes hole conduction, resulting in a shift of the off-state current for the p-branch. The band bending becomes more pronounced as V_DS is incremented negatively, directly influencing the hole injection. Additionally, V_DS also influences the entire band under the effect of V_TG, inducing band bending on the source side, which enhances the tunneling current and ultimately supports charge carrier conduction.

Figure 4

Two-top-gated nanowire array-based device with a SiO₂ shell. (a) Cross-sectional schematic layout of the two-top-gated device with corresponding voltage naming schemes. (b) SEM micrograph of the measured device. (c) Transfer characteristics for unipolar operation. Unipolar device characteristics modulation with auxiliary back gating leads to enhanced transfer characteristics of the device showing (d) n-type conduction and (e) p-type conduction under the influence of supplementary back gating.

Figure 5

Improved unipolar two-top-gated device characteristics of a nanowire array-based device. (a) Top-view SEM micrograph of the two-top-gated nanowire array device with the source-drain contact pads, hBN flake transferred on top, and the broader CG and PG structures; (b) Cross-sectional HAADF-STEM micrograph of the sectioned nanowire. (c) Corresponding superimposed EDXS-based element distribution map of the device. The device structure shows the presence of a buried oxide layer under the silicon nanowire. 6–7 nm of SiO₂ serves as the primary dielectric layer, while hBN is present as an additional passivating and encapsulating layer. Ti and Al metal stacks serve as the gate electrode on top of the nanowire. (d) Cross-sectional schematic of the device including the voltage naming conventions used in this work. (e) Two-top-gated unipolar transfer characteristics of the device consisting of a nanowire array of 20 nanowires with a SiO₂ shell. The length and width of the nanowires are 2.3 μm and 25 nm, respectively.

Figure 6

Normalized pn symmetry scores for various RFET studies over the past decade are presented,^,,,− where a higher score indicates closer proximity to the ideal pn symmetry value of 1. The device from this work is highlighted in red, demonstrating its superior symmetry performance compared to other benchmark RFET devices.

Figure 7

Benchmark comparison of RFET devices in terms of on-current versus on–off ratio for (a) n-type and (b) p-type configurations. The performance of the device fabricated in this work is compared to other RFET devices developed over the past decade, including foundational studies. The star symbol represents the best device result from this work, while square symbols indicate RFETs based on Si nanowire channels,^,,,− triangles denote Ge-based RFETs,^, and pentagons represent SiGe-based RFETs.^,.