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. 2025 Jun 25;11(1):129.
doi: 10.1038/s41378-025-00979-3.

Wafer-scale fabrication of solid-state nanopore array with a novel SpacerX process

Affiliations

Wafer-scale fabrication of solid-state nanopore array with a novel SpacerX process

Lihuan Zhao et al. Microsyst Nanoeng. .

Abstract

Solid-state nanopores (SSNPs) have emerged as a transformative platform in nanotechnology and biotechnology, yet their application is limited by the lack of cost-effective, reproducible fabrication technology. Here, we introduce a novel SpacerX process for wafer-scale fabrication of well-ordered nanopore arrays inspired by spacer patterning used in the standard semiconductor manufacturing process. This technique is intrinsically scalable and features tunable nanopore dimensions, with an open-pore rate exceeding 99.9%, even in an academic cleanroom. We successfully demonstrated a silicon nitride (Si3N4) nanopore array with a diameter of ~30 nm, non-uniformity below 10%, and spacing of 10 μm. By further reducing the spacer size, the nanopore diameter can be minimized to 10 nm. We fabricated multi-pore devices and showed that dual-pore devices offer higher detection throughput for DNA molecules. The SpacerX process only involves two ultraviolet lithography steps with one mask, and can be readily adopted by commercial foundries, thus opening the possibility of mass-producing sub-10 nm SSNPs at extremely low cost.

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Conflict of interest statement

Conflict of interest: The authors declare no competing interests. Ethics approval and consent to participate: Not applicable.

Figures

Fig. 1
Fig. 1
Schematic illustration of the Si3N4 nanopore array fabrication process
Fig. 2
Fig. 2. Development process scheme of the spacer morphology and etching models.
a The top view SEM image of the spacer s with a 5 μm spacing. b The sectional view of the spacer. ce The SEM images of the different etching time. f Etching models of the spacer. The scale bars are a 1 μm, be 100 nm
Fig. 3
Fig. 3. The SEM images of the step-by-step processes of Wafer 1.
The α-Si layer strip (a), coated with Al2O3 sidewalls (b) and re-coated with α-Si (c). ac were obtained from dummy wafers. d Top view of Al2O3 nanostrip structure after CMP. e The structure after Step 3 of Fig. 1 was repeated (wafer tilted by 20°). Top view of the SpacerX (f) and cross-sections at Sections 1 g and 2 h. The top view SEM image of the SpacerX after etching i, and the wafer tilted by 20° (j). Si3N4 nanopore array (k), a single nanopore (l), and the enlarged nanopore. The nanopore by reducing the etching time to 60% (m) and increasing the etching time to 150% (n). The scale bars are aj 100 nm, k 50 μm, l 500 nm, the enlarged image of l, m and n 100 nm
Fig. 4
Fig. 4. Fabrication process optimization.
a Schematic diagram of the SpacerX etching model. b Statistical chart of the L and W of the nanopores of Wafer 1, with an inset illustrating the L and W. SEM cross-sectional images of the BSP and USP (c, d), and the corresponding SEM image of the nanopores (e) of Wafer 2. SEM cross-sectional images of the BSP and USP (f, g), and the corresponding SEM image of the nanopore (h) of Wafer 3. i Statistical chart of the L and W of the nanopores of Wafer 3, with an inset illustrating the L and W. Film materials: c and f correspond to Fig. 3g; d and g correspond to Fig. 3h; e and h correspond to Fig. 3l. All of the SEM image scale bars are 100 nm
Fig. 5
Fig. 5. Nanopore shrinkage strategy.
a Schematic diagram of the nanopore shrinking process. The SEM images top view (b, c) sectional view of the narrowed SpacerX. d The SEM image of the nanopore fabricated by the shrinking SpacerX. Film materials: c corresponds to Fig. 3g; d corresponds to Fig. 3l. All of the SEM image scale bars are 100 nm
Fig. 6
Fig. 6. The customized design scheme for fabricating the Si3N4 nanopore devices.
a Fabrication process illustration of the Si3N4 nanopore devices. The SEM images of single-pore (b) and dual-pore (c) window areas. All of the SEM image scale bars are 10 μm
Fig. 7
Fig. 7. The conductivity of Si3N4 nanopore devices and their detection signals of circular phiX174 viral DNA.
a The conductivities of single and dual-pore devices, with the bottom-right inset displaying their current-voltage curves, and the top-left inset showing the image of a single Si3N4 nanopore device. b The translocation current signals of circular phiX174 viral DNA through single and dual-pore devices. The bottom inset shows the schematic illustrations of the DNA translocating through the Si3N4 nanopore and a typical event. Scatter plots of translocation events and corresponding histogram of dwell time versus peak current of single (c) and dual-pore (d) devices, respectively. All experiments were performed in 2 M LiCl, pH 8.0, at 140 mV

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