GaN HEMT Oscillators with Buffers

Abstract

With their superior switching speed, GaN high-electron-mobility transistors (HEMTs) enable high power density, reduce energy losses, and increase power efficiency in a wide range of applications, such as power electronics, due to their high breakdown voltage. GaN-HEMT devices are subject to long-term reliability due to the self-heating effect and lattice mismatch between the SiC substrate and the GaN. Depletion-mode GaN HEMTs are utilized for radio frequency applications, and this work investigates three wide-bandgap (WBG) GaN HEMT fixed-frequency oscillators with output buffers. The first GaN-on-SiC HEMT oscillator consists of an HEMT amplifier with an LC feedback network. With the supply voltage of 0.8 V, the single-ended GaN oscillator can generate a signal at 8.85 GHz, and it also supplies output power of 2.4 dBm with a buffer supply of 3.0 V. At 1 MHz frequency offset from the carrier, the phase noise is -124.8 dBc/Hz, and the figure of merit (FOM) of the oscillator is -199.8 dBc/Hz. After the previous study, the hot-carrier stressed RF performance of the GaN oscillator is studied, and the oscillator was subject to a drain supply of 8 V for a stressing step time equal to 30 min and measured at the supply voltage of 0.8 V after the step operation for performance benchmark. Stress study indicates the power oscillator with buffer is a good structure for a reliable structure by operating the oscillator core at low supply and the buffer at high supply. The second balanced oscillator can generate a differential signal. The feedback filter consists of a left-handed transmission-line LC network by cascading three unit cells. At a 1 MHz frequency offset from the carrier of 3.818 GHz, the phase noise is -131.73 dBc/Hz, and the FOM of the 2nd oscillator is -188.4 dBc/Hz. High supply voltage operation shows phase noise degradation. The third GaN cross-coupled VCO uses 8-shaped inductors. The VCO uses a pair of drain inductors to improve the Q-factor of the LC tank, and it uses 8-shaped inductors for magnetic coupling noise suppression. At the VCO-core supply of 1.3 V and high buffer supply, the FOM at 6.397 GHz is -190.09 dBc/Hz. This work enhances the design techniques for reliable GaN HEMT oscillators and knowledge to design high-performance circuits.

Keywords: GaN HEMT power oscillator; buffer; figure of merit; left-handed transmission line; phase noise; reliability.

Figure 1

(a) Block diagram of a feedback oscillator with an amplifier H. (b) Schematic and (c) equivalent circuit of the first HEMT oscillator.

Figure 2

Chip micrograph for the HEMT oscillator. 2 mm × 1 mm.

Figure 3

Measured I-V curve of buffer HEMT. Size: L = 0.25 μm, W = 75 μm, Number of fingers = 2.

Figure 4

Measured (a) expanded spectrum and (b) full-span spectrum. V_DD = 0.8 V, V_G1 = −2.4 V, V_B = 3 V, and V_G2 = −2 V.

Figure 5

Measured phase noise. V_DD = 0.8 V, V_G1 = −2.4 V, V_B = 3 V, and V_G2 = −2 V. A red 1/f ³ guideline is used for reference.

Figure 6

Measured output power and frequency versus V_DD. V_G1 = −2.4 V, V_B = 3 V, and V_G2 = −2 V.

Figure 7

Measured buffer bias effect. V_DD = 0.8 V, V_G1 = −2.4 V, V_B = 0.8~4 V, and V_G2 = −2 V.

Figure 8

FOM and FOM_p versus V_DD. V_DD = 0.8~3 V, V_G1 = −2.4 V, V_B = 3 V, and V_G2 = −2 V.

Figure 9

Measured oscillation frequency versus V_DD. V_B = 3 V, V_G1 = −2.4, and V_G2 = −2 V.

Figure 10

(a) Measured output power versus V_DD. (b) Measured power consumption versus V_DD. V_B = 3 V, V_G1 = −2.4, and V_G2 = −2 V.

Figure 11

Measured phase noise versus step stress. (a) V_DD = 0.8 V, V_B = 3 V, V_G1 = −2.4, and V_G2 = −2 V. Measured on chip 1. (b) V_DD = 1 V, V_B = 3 V, V_G1 = −2.4, V_G2 = −2 V. (c) V_DD = 3 V, V_B = 3 V, V_G1 = −2.4, and V_G2 = −2 V.

Figure 12

Measured phase noise at 1 MHz offset frequency versus V_DD. V_B = 3 V, V_G1 = −2.4, and V_G2 = −2 V. Measured on chip 1.

Figure 13

Calculated FOM. V_B = 3 V, V_G1 = −2.4, and V_G2 = −2 V. Measured on chip 1.

Figure 14

(a) Measured fresh and stressed I-V of buffer FET versus V_B. Measured on chip 2. V_G2 = −1, −2, and −3 V. Blue: fresh, and red: post-stress. (b). Measured oscillation frequency versus V_B. V_DD = 0.75 V, V_G1 = −2.4, and V_G2 = −2 V. Measured on chip 2. (c) Measured phase noise versus step stress. V_DD = 0.75 V, V_B = 2 V, V_G1 = −2.4, and V_G2 = −2 V. Measured on chip 2.

Figure 15

(a) Right-handed T-lines and (b) left-handed T-lines.

Figure 16

Schematic (a) and equivalent circuit (b) of the second oscillator.

Figure 17

(a) Simulated input impedance at the drain of M₁. V_DD = 2 V, V_G1 = −2 V, V_B = 2 V, and V_G2 = −2 V. (b) Simulated inductance and Q-factor of inductor L₁ (= L₂ = L₃).

Figure 18

Chip micrograph for the HEMT oscillator. 2 mm × 1 mm.

Figure 19

Measured output voltages. V_DD = 0.6 V, V_G1 = −2.1 V, V_B = 0.8 V, and V_G2 = −2.1 V.

Figure 20

Measured spectrum. V_DD = 1.4 V, V_G1 = −2.2 V, V_B = 0.8 V, and V_G2 = −2.3 V.

Figure 21

Measured phase noise. V_DD = 0.6–2 V, V_G1 = −2.1 V, V_B = 0.8 V, and V_G2 = −2.1 V. The green line is used as a guideline for phase noise due to thermal noise.

Figure 22

Measured frequency, phase noise, output power, and current consumption vs. V_DD. V_DD = 0.6~2 V, V_G1 = −2.2 V, V_B = 0.8 V, and V_G2 = −2.3 V.

Figure 23

Measured power consumption and output power of the buffer versus V_B. V_DD = 1.4 V, V_G1 = −2.1 V, V_B = 0.2 ~ 2 V, and V_G2 = −2.3 V.

Figure 24

Measured output power, oscillation frequency, and core current consumption versus biased time. V_DD = 15 V, V_G1= −2.1 V, V_B = 0.8 V, and V_G2 = −2.1 V.

Figure 25

(a) Measured phase noises for t_bias = 0, 30, 60 min. V_DD = 0.6 V, V_G1 = −2.1 V, V_B = 0.8 V, and V_G2 = −2.1 V. (b) Measured post-stress phase noises at 1 MHz offset frequency. V_DD = 0.6–2 V, V_G1 = −2.1 V, V_B = 0.8 V, and V_G2 = −2.1 V.

Figure 26

Circuit schematic of the third designed GaN FFO.

Figure 27

Equivalent circuit for the dual resonant network.

Figure 28

(a) Simulated phase noise. Red: deleted (L₂, L₃). (b) Impedances between A and B nodes. Purple/Red tank impedance with/without (L₂, L₃). Blue impedance between C and D nodes.

Figure 29

Simulated waveforms and frequency-domain analysis of the oscillator: (a) drain (V_D) and gate (V_G) voltage waveforms of transistor M₁; (b) drain current (I_D) waveform of transistor M₁; (c) DFT results of drain voltage (V_D), drain current (I_D), and impedance magnitude between nodes A and B.

Figure 30

Simulated drain voltage V_out1 waveform (a,b), DFT analysis of voltage (VC) and current (IC) at node C, and the impedance magnitude between nodes C and D (Z_CD), based on the oscillator schematic in Figure 26. V_DD = 1.3 V, V_bias = −1.6 V, V_DB = 5 V, and V_B = −2 V.

Figure 31

(a) Layout of L₂. (b) Layout of L₁. (c) Simulated inductance and Q-factor.

Figure 32

Chip photo of FFO.

Figure 33

Measured (a) full-span spectrum and (b) expanded spectrum of the VCO. V_DD = 1.3 V, V_bias = −1.6 V, V_DB = 5 V, and V_B = −2 V.

Figure 34

(a) Measured phase noise of the GaN FFO. V_DD = 1 V, V_bias= −1.6 V, V_DB = 5 V, and V_B = −2 V. (b). Measured phase noise of the GaN FFO. V_DD = 1.3 V, V_bias = −1.6 V, V_DB = 5 V, and V_B = −2 V.

Figure 35

Measured output voltages of the GaN FFO. V_DD = 1.3 V, V_DB = 5 V, V_B = −2 V, and V_bias = −1.6 V.