Two-Dimensional Materials for Raman Thermometry on Power Electronic Devices

Abstract

Raman thermometry is a powerful technique for sub-microscale thermal measurements on semiconductor-based devices, provided that the active region remains accessible and is not obscured by metallization. Since pure metals do not exhibit Raman scattering, traditional Raman thermometry becomes ineffective in such cases. To overcome this limitation, we propose the use of atomically thin Two-Dimensional materials as local temperature sensors. These materials generate Raman spectra at the nanoscale, enabling highly precise absolute surface temperature measurements. In this study, we investigate the feasibility and effectiveness of this approach by applying it to power devices, including a calibrated gold resistor and an SiC Junction Barrier Schottky (JBS) diode. We assess the processing challenges and measurement reliability of 2D materials for thermal characterization. To validate our findings, we complement Raman thermometry with thermoreflectance measurements, which are well suited for metallized surfaces. For example, on the serpentine resistor, Raman thermometry applied to the 2D material yielded a thermal resistance of 22.099 °C/W, while thermoreflectance on the metallic surface measured 21.898 °C/W. This close agreement suggests good thermal conductance at the metal/2D material interface. The results demonstrate the potential of integrating 2D materials as effective nanoscale temperature probes, offering new insights into thermal management strategies for advanced electronic components. Additionally, thermal simulations are conducted to further analyze the thermal response of these devices under operational conditions. Furthermore, we investigate two 2D material integration methods, transfer and direct growth, and evaluate them through measured thermal resistances for the SiC JBS diode, highlighting the influence of the deposition technique on thermal performance.

Keywords: 2D materials; 3D finite elements simulations; Raman spectrometry; power electronics; thermal sensors; thermoreflectance.

Figure 1

Schematic of junction temperature measurement in GaN-based HEMT devices using Raman spectroscopy: (left) without 2D material, (right) with a 2D material layer deposited above the gate region.

Figure 2

Energy spectrum and atomic crystal structures for monolayers of different two-dimensional (2D) materials. From left to right: boron nitride (h-BN), transition metal dichalcogenides (TMDCs), black phosphorous, and graphene. Adapted from [11].

Figure 3

Experimental steps of the 2D material transfer (left) and the direct synthesis and growth on the target device (right).

Figure 4

PDMS stamp with a surface contact area of approximatively 700 × 900 µm².

Figure 5

PtSe₂ patch transferred on aluminum surface of an SiC diode (left) and Raman mapping of Eg peak intensity (right).

Figure 6

PtSe₂ patches on an SiC diode using the “2D growth” method.

Figure 7

Raman signature during the PtSe₂ patches manufacturing, using the transfer method (left) and the growth method (right).

Figure 8

Schematic of thermal and electric setup for Raman temperature measurements.

Figure 9

Optical view of the Raman measurements with electrical probes.

Figure 10

Schematic of the thermoreflectance setup.

Figure 11

Variation of the thermal coefficient of reflectance $C_{th}$ as a function of wavelength for different materials.

Figure 12

SiC diode wafer under test in thermoreflectance setup.

Figure 13

Optical image of the die with 16 resistors. The resistor used is highlighted in yellow and wires are connected to electrical setup.

Figure 14

Optical images of the 32/64 resistor after the PtSe₂ transfer by PDMS technique (left); zoom of the PtSe₂ patch on the resistor with the laser spot for thermal Raman measurement (right).

Figure 15

Thermal calibration curve with the AS/S Raman peak intensity ratio method. 50X, 2400 lines/mm, Notch filter, static regular, 0.25 mW, 30 s, 4 frames.

Figure 16

Thermal calibration curve with the Raman peak shift method. 50X, 3000 lines/mm, edge filter, static regular, 0.25 mW, 30 s, 2 frames.

Figure 17

Thermoreflectance calibration image of the 32 × 64 resistor (left); thermoreflectance ΔT (°C) distribution of the 32 × 64 resistor for a dissipated power of 5.9 W (right).

Figure 18

Dimensions of the different layers for the geometry of the 32 × 64 resistor.

Figure 19

Steady state thermal simulation of the 32 × 64 resistor.

Figure 20

Temperature calibration (left); dissipated power measurements (right).

Figure 21

Infrared measurement on 32 × 64 resistor, emissivity of materials (left); temperature mapping for 5.7 W dissipated at Tcase = 50 °C (right).

Figure 22

Infrared measurement on 32 × 64 resistor with coating.

Figure 23

Temperature extraction with the E_g Raman peak shift, AS/S E_g peak intensity ratio, thermoreflectance, thermal simulation, electrical method, and infrared measurement on the 32 × 64 resistor at T_case = 50 °C.

Figure 24

Temperature extraction with the A_1g Raman peak shift, AS/S A_1g peak intensity ratio, thermoreflectance, thermal simulation, electrical method, and infrared measurement on the 32 × 64 resistor at T_case = 50 °C.

Figure 25

Optical image of an SiC diode (left); cross-sectional schematic of the SiC diode (right).

Figure 26

Optical image of the SiC JBS diode with grown 2D material using the thermoreflectance CCD camera.

Figure 27

Calibration Image of the SiC JBS diode using a wavelength of 780 nm.

Figure 28

Temperature vs. dissipated power for grown patch and aluminum metallization of the SiC JBS diode.

Figure 29

Optical image of an SiC JBS diode without 2D material.

Figure 30

Temperature vs. dissipated power of the SiC JBS diode without 2D material.

Figure 31

Thermal calibration curve with the Eg Raman peak shift method for grown PtSe₂ patches on the SiC diode. 50XLF, 3000 lines/mm, edge filter, static regular, 0.25 mW, 30 s, 4 frames.

Figure 32

Temperature extraction with the Eg Raman peak shift (orange dots) for grown patch on SiC diode vs. thermoreflectance measurements (blue dots).

Figure 33

Thermal calibration curve with the Eg Raman peak shift method for transferred PtSe₂ patches on the SiC diode. 50XLF, 3000 lines/mm, edge filter, static regular, 0.25 mW, 30 s, 4 frames.

Figure 34

Temperature extraction with the Eg Raman peak shift for transferred patch (blue dots) and etched patch (red dots) on power SiC diode, from 0 to 6 A at Tcase = 50 °C.

Figure 35

The Schottky-JBS diode mounted on the AlN support.

Figure 36

Temperature variation vs. power for thermal paste with k = 2.5 W/mK (left) and k = 0.5 W/mK (right).

Figure 37

X radiography of the die attach for the two samples; presence of important voids for the etch patch one (right).