Bi2O2Se-Based Monolithic Floating-Gate Nonvolatile Memory with Enhanced Charge Retention and Switching Performance

Abstract

The continuous scaling of conventional floating-gate memories faces major challenges due to charge leakage and complex multilayer architectures. Here, we report a monolithic nonvolatile memory (NVM) device constructed using a single 2D material, Bi₂O₂Se, that integrates channel, charge storage, and tunneling functions within the same material system. Upon UV-ozone treatment, semiconducting Bi₂O₂Se (s-BOS) forms a conformal and crystalline β-Bi₂SeO₅ shell. Subsequent thermal annealing introduces selenium vacancies into the core, converting it to metallic Bi₂O₂Se (m-BOS), which serves as a floating-gate capable of efficient charge trapping, while the crystalline BOS oxide shell provides robust tunneling insulation and suppresses leakage. This monolithic structure integrates channel (s-BOS), storage (m-BOS), and tunneling functions (BOS oxide) within a single material system. The devices exhibit a large memory window, a high charge storage density (∼5 × 10¹³ cm^-2), and a current ON/OFF ratio exceeding 10⁸. They also show fast programming/erasing with ±12 V, 100 ms pulses, robust endurance over 2000 cycles, and charge retention exceeding 10⁴ seconds. Compared with other 2D NVMs employing separate materials for each functional layer, this single-material platform enables simplified fabrication and improved scalability in the 2D memory device design.

Keywords: 2D memory; Bi2O2Se; low-power device; monolithic nonvolatile memory; process simplification.

1

Schematic illustration and cross-sectional characterization of the BOS-based floating-gate nonvolatile memory device. Cross-sectional STEM images reveal a crystalline BOS oxide shell encapsulating the s-BOS core. The integrated structure functions as channel (s-BOS), tunneling layer (BOS oxide), and floating-gate (m-BOS) within a single material platform.

2

Electronic, vibrational, and structural characterization of the s-BOS/oxide heterostructure. (a) Transfer curves of s-BOS FETs annealed at different temperatures, indicating Se vacancy-induced n-type doping. (b) Raman spectra reveal a redshift and broadening of the A_1g mode after oxidation. (c) BOS oxide thickness as a function of oxidation time and temperature, showing thermally activated growth. The approach for thickness measurement is stated in Supporting Information 5.

3

STEM characterization of the s-BOS/oxide heterostructure and DFT calculations. (a) Atomic-resolution STEM image showing a BOS oxide atop s-BOS. (b) Atomic structures of pristine s-BOS, m-BOS with selenium vacancies, and the native BOS oxide. The purple, red, and yellow atoms represent Bi, O, and Se, respectively. (c) Density of states (DOS) for s-BOS, the BOS oxide, and m-BOS with 3.1% selenium vacancies. Band gap regions are shaded in gray. The Fermi level of m-BOS is marked by a black dashed line, showing an n-type degenerate semiconductor. The valence band maximum of s-BOS is set to energy zero, while the band energies of the BOS oxide and s-BOS are aligned based on their experimentally measured work functions.

4

Electronic properties of the s-BOS FET and BOS NVM structure. (a) Optical image of a BOS NVM device arranged in a cross structure. A control device of s-BOS back-gate FET is fabricated on the same s-BOS crystal, located in the right-hand side of the BOS NVM device. (b) Transfer characteristics of the back-gate FET, with inset showing linear I–V output curves. (c) Schematic of the BOS NVM device structure incorporating the BOS floating-gate stack above a HfO₂/TiN substrate. (d) Energy band diagram and electron affinity of the corresponding layers. The bandgap values are as follows: BOS, 1.15 eV; BOS oxide, 3.7 eV; HfO₂ (grown by PE-ALD), ∼5.8 eV. (e) Process flow for the whole BOS NVM device. Two pieces of s-BOS on mica are needed; one is for the m-BOS/oxide core–shell structure and the other is for the channel.

5

Memory switching characteristics and charge transfer mechanisms of the BOS NVM device. (a) Transfer curves under increasing control gate voltage V_CG (±6 to ±12 V), showing widening memory window. Inset: memory window versus gate sweep amplitude. (b) Dynamic switching behavior with fixed PRG pulse (+12 V, 2 s) and varying ERS pulse durations (−12 V, 0.5 ms to 2 s), illustrating progressive threshold voltage recovery. (c, d) Schematic energy band diagrams depicting charge injection during programming (c) and erasing (d) via Fowler–Nordheim and field-assisted tunneling through the BOS oxide barrier.

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Endurance and retention performance of the BOS NVM device. (a) Endurance test over 2000 PRG/ERS cycles (±12 V, 100 ms). (b) Retention characteristics of a control device without the BOS oxide shell showing rapid current degradation within 200 s. (c) Retention test of the device demonstrating stable I_on/I_off ≈ 10⁶ over 10⁴ s.