High Performance Multiple Inversion Layer Selective Buried Triple Gate Vertical Trench Power MOSFET

Abstract

This paper analyses the various properties that governs a power MOSFET for a novel and unique vertical triple gate selective buried trench power MOSFET. Our recent work consists of a MOSFET having two lateral selective buried gates and a single vertical trench gate facing the drift region, resulting in a Triple gate power MOSFET (TGSBTPMOS). This unique combination of three gates results in significantly high device ON-state current and ultra-low ON resistance of about 0.38 mΩ.cm² in the voltage class of 78.8 V. Our proposed device has multiple inversion layers, which helps in enlarging the channel width and on-current of the device, resulting in better static state and switching performance compared to the conventional power MOSFET. 2-D Silvaco ATLAS simulation output has revealed the outperformance of the proposed device in all the areas governing power MOSFET, i.e., gate-to-drain charge (Qgd), device transfer and output (I-V) characteristic, Balliga's Figure of Merits (FOM1 and FOM2). Furthermore, the proposed device achieves 4.86 orders of magnitude improvement in FOM1, 68.85% in Ron.sp, 94.54% in Qgd, and 98.34% in FOM2. Our proposed device is an enhancement in the existing state of the art and competes with the reported power MOSFET structure in terms of performance.

Fig. 1

Cross-sectional depiction of triple gate selective buried vertical trench power MOSFET (TGSBTPMOS).

Fig. 2

Conventional trench power MOSFET (CTPMOS).

Fig. 3

Device electrical operation and inversion layer formation in the conducting phase.

Fig. 4

ON-state device operation mechanism analysis in the Proposed and Conventional device at Vds = 10 V, Vgs = 12 V: (a) and (b) Electron concentration distribution in the proposed device and Conv. MOSFET.

Fig. 5

(a) Breakdown (off state) voltage characteristic (b) Input Characteristics (c) Output Characteristics (d) variation of device ON resistance with applied gate voltage, for proposed and conventional device.

Fig. 6

Drain current (vs. Vgs) in the logarithm scale (form) for proposed and conventional device.

Fig. 7

Electric field of the two devices before breakdown.

Fig. 8

Impact ionization of the two devices before breakdown.

Fig. 9

Gate charge simulation output with circuit.

Fig. 10

Mixed mode circuit simulation result for proposed and conventional device, with detailed view.

Fig. 11

Depletion region depth representation w.r.t buried gate and its value at Vds = 2 V, 15 V and 30 V for Cgd measurements.

Fig. 12

Dependence of depletion region depth (d) formation at drain voltage vs. gate-drain Capacitance (Cgd) for the proposed and conventional MOSFET.

Fig. 13

Change in breakdown voltage along with p-body doping in the proposed and the conventional (CTPMOS) structures.

Fig. 14

Various device regions’ hole concentration distribution for the TGSBTPMOS and CTPMOS structures, in the vertical position.

Fig. 15

Specific ON-resistance (Ron.sp) in relation to breakdown voltage (BV), juxtaposed with the ideal silicon limit line of the projected (TGSBTPMOS) device, associated to other all types power transistors, alongside the equivalent Baliga’s FOM1.

Fig. 16

Benchmarking of Vth with IONmax and RON.SP of the TGSBTPMOS against various power transistors.

Fig. 17

Improvement in the performance of TGSBTPMOS over conventional device.

Fig. 18

Process flow (fabrication) for the proposed TGSBTPMOS device.