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. 2025 Oct 16;15(1):36253.
doi: 10.1038/s41598-025-20146-y.

Efficient FPGA implementation of polar codes-based information reconciliation for quantum key distribution

Lianye Liao  1   2 , Xinyi Wu  1   2 , Ye Chen  1   2 , Xiaodong Fan  1   2 , Zhiyu Tian  1   2 , Jinquan Huang  1   2   3 , Tonglin Mu  1   2 , Junran Guo  1   2 , Minjie Liu  1   2 , Bo Liu  3 , Shihai Sun  4   5
Affiliations

Efficient FPGA implementation of polar codes-based information reconciliation for quantum key distribution

Lianye Liao et al. Sci Rep. .

Abstract

Quantum key distribution (QKD) leverages the principles of quantum mechanics to generate unconditionally secure keys for remote communication, even in the presence of an eavesdropper with unlimited computational power. A critical component of QKD is information reconciliation (IR), which corrects bit errors introduced by system imperfections and channel noise, ensuring the integrity of the shared key. Polar codes-based IR schemes have attracted considerable attention due to their near-Shannon-limit performance and low computational complexity. However, existing implementations primarily rely on CPUs or GPUs, which are suboptimal in terms of performance and energy efficiency. Here, we present a hardware accelerator designed specifically for discrete variable QKD (DV-QKD), targeting polar codes-based IR and implemented on a cost-effective FPGA platform. Our design achieves high throughput and scalability by employing a module-level pipeline parallel structure, a fully parallelized decoding strategy, and a hybrid memory architecture. This approach enhances decoder efficiency and optimizes resource utilization. On this platform, we demonstrate an IR throughput of 35.33 Mbps for a block size of [Formula: see text], providing a real-time, cost-efficient solution that significantly enhances the performance of QKD systems.

Keywords: Discrete variable quantum key distribution (DV-QKD); Field programmable gate array (FPGA); Information reconciliation (IR); Polar codes.

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Conflict of interest statement

Declarations. Competing interests: The authors declare that they have no competing interests.

Figures

Fig. 1
Fig. 1
Polar codes decoder for a block length of 8.
Fig. 2
Fig. 2
Polar codes-based AIR scheme.
Fig. 3
Fig. 3
Decoding binary tree structure of formula image.
Fig. 4
Fig. 4
Compression and decompression conversion diagram for a block length of 8.
Fig. 5
Fig. 5
Hardware implementation architecture diagram of the SCL decoder.
Fig. 6
Fig. 6
Module-level pipeline timing diagram.
Fig. 7
Fig. 7
LLR data path in the formula image-bit decoder.
Fig. 8
Fig. 8
Splitting diagram of formula image decoder at Rate1 node for formula image.
Fig. 9
Fig. 9
IR reconciliation efficiency and throughput for QBER formula image and formula image.
See this image and copyright information in PMC

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